1. Field of the Invention
This invention relates to a method of manufacturing a semiconductor device having an SOI (Semiconductor On Insulator) structure.
2. Description of Related Arts
A conventional method of manufacturing a semiconductor device having an SOI structure will first be described using FIGS. 27 through 51. FIG. 27 is a sectional view showing a conventional semiconductor device having an SOI structure. FIGS. 28 through 51 are sectional views showing the first through 24th steps in a process for manufacturing a conventional semiconductor device having SOI structure shown in FIG. 27.
First, the structure of a conventional semiconductor device having an SOI structure will be described using FIG. 27.
A buried oxide film 2 is formed on the main surface of a silicon substrate. Formed on this buried oxide film 2 is a semiconductor layer (hereinafter referred to simply as "SOI layer") 3. Formed on the SOI layer 3 are an nMOS transistor 14 and a pMOS transistor 15. The nMOS transistor 14 has an n.sup.- region 5a and an n.sup.+ region 5b formed in the SOI layer 3, a gate oxide film 20, and a gate electrode 8. The pMOS transistor 15 has a p.sup.- region 6a and a p.sup.+ region 6b formed in the SOI layer 3, a gate oxide film 20, and a gate electrode 8.
Titanium silicide layers 10 are formed on the surface of the n.sup.+ region 5b, the surface of the p.sup.+ region 6b, and the upper surface of the gate electrode 8. Further, the sidewall of the gate electrode 8 is formed with a sidewall insulating layer 16.
The nMOS transistor 14 and pMOS transistor 15 are isolated by an isolating oxide film 4 selectively formed on the SOI layer 3. The lateral end of the SOI layer 3 having the nMOS transistor 14 formed therein is formed with a high concentration impurity region 13 for element isolation. In this case, a high concentration p-type impurity is contained in this high concentration impurity region 13.
An interlayer dielectric 9 is formed to cover the SOI layer 3. This interlayer dielectric 9 is provided with a contact hole 11 at a predetermined position. And formed in this contact hole 11 and on the interlayer dielectric 9 is a metal electrode 12.
Next, using FIGS. 28 through 51, a description will be given of a method of manufacturing a conventional semiconductor device of SOI structure described above.
Referring to FIG. 28, a burred oxide film 2 and an SOI layer 3 are formed on the main surface of a silicon substrate 1 by a conventional method. A surface of SOI layer 3 is oxidized in the condition of 950.degree. C. wet ambience to form an oxide film 20 having a thickness of about 300 .ANG.. Formed on this oxide film 20 by using the CVD (Chemical Vapor deposition) method is a nitride film 21 having a thickness of about 500 .ANG..
Subsequently, a resist is applied to the nitride film 21 and patterned in a predetermined configuration. Thereby, as shown in FIG. 29, a resist pattern 22a is formed. Further, a resist pattern 22b is formed to cover the region where the pMOS transistor 15 is to be formed. And, as shown in FIG. 30, using the resist patterns 22b and 22a as masks, boron (B) ions are implanted into the SOI layer 3. The conditions are 3.times.10.sup.13 /cm.sup.2, 20 KeV.
Next, referring to 31, subsequent to the removal of resist patterns 22a and 22b, a heat treatment is applied to the SOI layer 3. Thereby, a p-type high concentration impurity region 13 is formed.
Next, referring to FIG. 32, a selective oxidation treatment is applied to the SOI layer 3 by using the nitride film 21 as a mask. The conditions for this selective oxidation treatment are 950.degree. C., 60 minutes in a wet ambience. In this manner, the isolating oxide film 4 is formed by a single selective oxidation treatment. Thereafter, as shown in FIG. 33, the nitride film 21 is removed as by hot phosphoric acid.
Next, referring to FIG. 34, a resist pattern 22c is formed to cover the region where the pMOS transistor 15 is be formed. Using this resist pattern 22c as a mask, boron (B) ions are implanted into the SOI layer 3. Thereby, channel doping for the nMOS transistor 14 is effected.
Next, referring to FIG. 35, subsequent to the removal of resist pattern 22c, a resist pattern 22d is formed to cover the region where the nMOS transistor 14 is to be formed. Using this resist pattern 22d as a mask, boron (B) ions are implanted into the SOI layer 3. Thereby, channel doping for the pMOS transistor 15 is effected.
Next, referring to FIG. 36, subsequent to the removal of resist pattern 22d, a polycrystalline silicon layer 8a having a thickness of about 3000 .ANG. is formed as by the CVD method. At this time, preferably, phosphorus (P) in an amount of about 1.times.10.sup.19 /cm.sup.3 or more is contained in this polycrystalline silicon layer 8a. A resist pattern 22e is formed on this polycrystalline silicon layer 8a. And using this resist pattern as a mask, the polycrystalline silicon layer 8a is etched. This results in forming a gate electrode 8, as shown in FIG. 37.
Next, referring to FIG. 38, a resist pattern 22f is formed to cover the region where the pMOS transistor 15 is to be formed. Using this resist pattern 22f as a mask, phosphorus (P) is implanted into the SOI layer 3. This results in forming an n.sup.- region 5a.
Next, referring to FIG. 39, subsequent to the removal of resist pattern 22f, a resist pattern 22g is formed to cover the region where the nMOS transistor 14 is to be formed. Using this resist pattern 22g as a mask, boron (B) is implanted into the SOI layer 3. This results in forming a p.sup.- region 6a.
Next, as shown in FIG. 40, TEOS (Tetra Ethyl Ortho Silicate) is used to form an oxide film (TEOS oxide film) 16a having a thickness of about 1500 .ANG.. Anisotropic etching is applied to this TEOS oxide film 16a. As shown in FIG. 41, this results in forming a sidewall insulating layer 16.
Next, referring to FIG. 42, a resist pattern 22h is formed to cover the region where the pMOS transistor 15 is to be formed. Using this resist pattern 22h as a mask, arsenic (As) is implanted into the SOI layer 3. This results in forming an n.sup.+ region 5b.
Next, referring to FIG. 43, subsequent to the removal of said resist pattern 22h, a resist pattern 22i is formed to cover the region where the pMOS transistor 15 is to be formed. Using this resist pattern 22i as a mask, boron (B) is implanted into the SOI layer 3. This results in forming a p.sup.+ region 6b.
Subsequently, the resist pattern 22i is removed. Thereby, as shown in FIG. 44, the pMOS and nMOS transistors 15 and 14, respectively, are formed.
Next, referring to FIG. 45, a Ti layer 10a having a thickness of about 200 .ANG. is formed as by sputtering. And this Ti layer 10a is subjected to lamp annealing at about 700.degree. C. for about 30 seconds. Thereby, the Ti layer 10a and the silicon layer thereunder are allowed to react with each other. And subsequent to the removal of the unreacted Ti layer 10a, a predetermined heat treatment is applied to thereby form a titanium silicide layer 10 as shown in FIG. 46.
Next, referring to FIG. 47, an interlayer dielectric 9 comprising a TEOS oxide film is formed. And formed on this interlayer dielectric 9, as shown FIG. 48, is a resist pattern 2j in predetermined pattern configuration. Using this resist pattern 22j as a mask, etching is applied to the interlayer dielectric 9. As shown in FIG. 49, this result in forming contact holes 11.
Next, referring to FIG. 50, a metal layer 12a containing A1 is formed as by sputtering. Formed on this metal layer 12a, as shown in FIG. 51, is a resist pattern 22k in predetermined pattern configuration. And using this resist pattern 22k as a mask, the metal layer 12a is patterned. This results in forming a semiconductor device shown in FIG. 27.
The pMOS and nMOS transistors 15 and 14 formed in the manner described above are isolated by the isolating oxide film 4. However, the formation of this isolating oxide film 4 by a single selective oxidation treatment as described above presents a problem, which will be described with reference to FIG. 52. FIG. 52 is an enlarged sectional view of the lateral end of the SOI layer 3 where the nMOS transistor 14 is formed in FIG. 27.
As shown in FIG. 52, in the case where the isolating oxide film 4 is formed by a single selective oxidation treatment, this leads to the formation of a thinned portion 3a of the SOI layer 3 under the isolating oxide film 4. The possession of this thinned portion 3a leads to the formation a parasitic transistor particularly at the end portion of the SOI layer 3 where the nMOS transistor 14 is formed. Thus, there has been problem that the subthreshold characteristics of MOS transistors are degraded.
The reason why the formation of the thinned portion 3a leads to the formation of a parasitic transistor in the thinned portion 3a will now be described in detail. Generally, the threshold voltage (Vth) of MOS transistors is expressed by the following formula. EQU Vth=V.sub.FB +2.phi..sub.B +Qs/Ci (1)
where V.sub.FB is the flat-band voltage; 2.phi..sub.B is the surface potential, Qs is the surface charge, and Ci is the gate oxide film capacity.
The V.sub.FB is expressed by a value which is obtained by subtracting the fixed charge/gate oxide film capacity from the difference in work function between the gate and the channel, and Qs is proportional to the product of the channel concentration and the depletion layer width. That is, when the fixed charge increases around the oxide film, the V.sub.FB decreases, and when the channel concentration or the depletion layer width decreases, the surface charge Qs decreases.
With the above taken into account, a description will be given of the reason why the formation of the thinned portion 3a leads to the formation of a parasitic MOS transistor having a low threshold voltage in the thinned portion 3a.
First, the V.sub.FB in the formula (1) will be described. Since the thinned portion 3a has a region which is in contact with the isolating oxide film 4, there is a high probability of the orientation of the crystals being deviated from &lt;100&gt; by the stress produced during the formation of the isolating oxide film 4. Therefore, the boundary 24 between the thinned portion 3a and the isolating oxide film 4 is formed with a fixed charge and interface state greater than those of the gate oxide film of the MOS transistor formed on the SOI layer 3. This fixed charge causes the V.sub.FB to take a value lower than the V.sub.FB of the intrinsic MOS transistor.
Next, Qs/Ci will be described. As the isolating oxide film 4 is formed, the impurity is absorbed from the thinned portion 3a located close to the isolating oxide film 4. As a result, the concentration of the impurity contained in the thinned portion 3a lowers. As described above, since Qs is proportional to the product of the channel concentration and the depletion layer width, the decrease of the concentration of the impurity contained in the thinned portion 3a corresponding to the channel leads to the decrease of the value of Qs. Further, in the region where thickness of the SOI layer decreases, the depletion layer width may be taken to be approximate to the thickness of the SOI layer 3. Therefore, in the thinned portion 3a, the depletion layer width is very small. Thus, the value of Qs is also very small.
Because of the above, V.sub.FB and Qs in the formula 1 are small, so that the value of Vth can be small. That is, a transistor having the thinned portion 3a as the channel and having lower threshold voltage (Vth) is formed. This transistor is to be the parasitic transistor. The formation in the thinned portion 3a of the SOI layer 3 of this parasitic transistor whose threshold voltage (Vth) is low means that the subthreshold characteristics of the MOS transistor formed on the SOI layer 3 is degraded.